Digital electronics is the invisible infrastructure of modern civilization, and it's all based on just two numbers: 0 and 1.
You will learn how to design, analyze, and simulate digital circuits, including a simple computer, starting from the smallest building blocks: transistors and logic gates.
After completing this course, you will be able to:
Thursday 1-2:15 is office hours.
Tuesday 1-2:15 is synchronous lab (circuit simulation).
Harris and Harris, Digital Design and Computer Architecture, 2nd edition, 2012 (2013 for ebook). The Emory library has unlimited copies!
We will use Canvas, Zoom, and a free circuit simulator during the synchronous sessions: https://www.edaplayground.com/. To use this website, I think your screen needs to be laptop-size or larger.
You will work with a randomly assigned lab partner during synchronous sessions. This is an opportunity to discuss the course material with a peer. Whether you find the material difficult or easy, your understanding will be bolstered through peer discussion. If you’re unavailable for a synchronous session, it’s okay; you can do the lab another time.
Recorded lectures are posted to Canvas. In these lectures, I frequently invite you to pause the video and complete the exercises. Watching someone do exercises doesn’t make you strong; you have to do the exercises yourself!
Lab reports: 22% (2% for each of 11 lab reports)
Projects: 38% (19% for each of 2 projects)
Tests: 40% (20% for each of 2 tests)
There’s no penalty for late lab reports and projects, though they must all be submitted by Dec. 3. However, lab reports help prepare you for the tests, so I hope you’ll submit them on time.
Some of the test questions and project details will be unique to you, based on your student ID. You may get help from any source on lab reports and projects, but the tests are solo activities.
Dates | Topics | Recommended Readings (skip VHDL in Ch. 4) | Recommended Exercises or Questions (Q) | Labs |
Aug. 19-25 | Binary arithmetic and logic gates | 1.4-1.5, 4.1.1, 4.2.7 | 1.53, 1.55, 1.57, 1.59. 1.61 | Lab 1 |
Aug. 26-Sept. 1 | Transistors and Boolean algebra | 1.6-1.8, 2.1-2.6, 4.2.1 | 1.85, 1.87, 2.1, 2.3, 2.27 | Lab 2 |
Sept. 2-8 | K maps and always blocks | 2.7-2.8, 4.2.5, 4.5.1, 4.5.2 | 2.25, 2.29, 2.31, 2.39, 2.41 | Lab 3 |
Sept. 9-15 | Sequential logic | 2.9, 3.1-3.3, 4.4 | 2.45, 3.1, 3.3, 3.5, 3.9 | Lab 4 |
Sept. 16-22 | Finite state machines | 3.4, 4.6 | 3.23, 3.25, 3.27, 3.31 | Lab 5 |
Sept. 23-29 | Timing diagrams | 3.5.1-3.5.3, 3.6 | 3.33, 3.35, Q2.1, Q3.1 | Project 1 |
Oct. 1 | Test 1 | |||
Oct. 2-6 | Adders | 5.2.1 | Project 1 | |
Oct. 7-13 | Arithmetic operations | 4.3, 5.2.2-5.4.1 | 5.29, 5.35, 5.37, 5.43, 5.45 | Lab 6 |
Oct. 14-20 | Memory and MIPS assembly language | 4.8, 5.5, 5.6.1, 6.1-6.2 | 5.51, 6.3, 6.5, 6.9, Q6.1 | Lab 7 |
Oct. 21-27 | Machine language | 6.3, 6.4.1-6.4.2 | 6.11, 6.13, 6.29 | Lab 8 |
Oct. 28-Nov. 3 | High-level code constructs | 6.4.3-6.4.6, 6.5 | 6.17, 6.25, Q6.5 | Lab 9 |
Nov. 4-10 | MIPS microarchitecture | 7.1-7.3 | 7.1, 7.3, 7.5 | Lab 10 |
Nov. 12 | Test 2 | |||
Nov. 13-17 | Serial communication | Lab 11 | ||
Nov. 18-24 | Quantum computing |